The present invention generally relates to semiconductor manufacturing and more particularly to fin field effect transistor (FinFET) devices having constrained source-drain epitaxial regions.
Complementary Metal-oxide-semiconductor (CMOS) technology is commonly used for fabricating field effect transistors (FETs) as part of advanced integrated circuits (IC), such as CPUs, memory, storage devices, and the like. Most common among these may be metal-oxide-semiconductor field effect transistors (MOSFET). In a typical MOSFET, a gate structure may be energized to create an electric field in an underlying channel region of a substrate, by which charge carriers are allowed to travel between a source region and a drain region. As ICs continue to scale downward in size, fin field effect transistors (FinFETs), sometimes referred to as tri-gate structures, may be potential candidates for the 14 nm node technology and beyond, primarily because FinFETs may offer better performance than planar FETs at the same power budget. FinFETs are three-dimensional (3D), fully depleted MOSFET devices having a plurality of fins formed from the substrate material. The gate structure may be located over the fins substantially covering the channel region, the portion of the fins not covered by the gate structure may define the source-drain regions of the device. Such architecture may allow for a more precise control of the conducting channel by the gate structure, significantly reducing the amount of current leakage when the device is in off state.